1. Field of the Invention
The present invention relates to a power supply system, and more particularly to a power supply including a self-excited flyback converter.
2. Description of the Related Art
(Basic Operation of Switching Power Supply Unit)
A power supply system using a commercial power supply usually includes an AC/DC converter for obtaining a DC output. As such an AC/DC converter, a self-excited flyback converter (or called a ringing choke converter (RCC)) has been widely used conventionally.
FIG. 5 is a circuit diagram showing a basic configuration of a conventional self-excited flyback converter. An isolating transformer 1 has a primary winding Np at the input side, a secondary winding Ns at the output side, and an auxiliary winding Nb at the primary side. The auxiliary winding Nb is a drive winding of a transistor 3 for controlling the gate voltage of a MOS-FET 2, a switching device. The input voltage E is a DC voltage obtained by rectifying an AC input voltage by a set of bridge diodes and by smoothing through an aluminum electrolytic capacitor. The input voltage E appears across the aluminum electrolytic capacitor. The bridge diodes and the aluminum electrolytic capacitor are not shown.
The input voltage E is applied across a terminal of the winding Np connected to the drain terminal of the MOS-FET 2 via a terminal of the primary winding Np, having its (+) side connected to the start of the winding Np and its (−) side connected to the source terminal of the MOS-FET 2. The auxiliary winding Nb is placed in the same polarity with the primary winding Np, and the secondary winding Ns is placed in the opposite polarity. The MOS-FET 2 has its gate terminal connected to starting resistors 4 and 5. In addition, a capacitor 6 and gate resistors 7 and 8 are connected across the gate terminal of the MOS-FET 2 and the start of the auxiliary winding Nb. A diode 9 is connected in parallel with the gate resistor 8 with its cathode facing to the auxiliary winding Nb side to control the turn-on and turn-off speed of the MOS-FET 2.
A capacitor 10 is connected across the base of the transistor 3 and the (−) side of the input voltage. A resistor 11 is connected across the auxiliary winding Nb and the base of the transistor 3, and constitutes a time constant circuit with the capacitor 10.
A photocoupler 12 has its collector connected to the gate of the MOS-FET 2 via a resistor 13 for limiting the current flowing through the photocoupler 12, and has its emitter connected to the base of the transistor 3. The isolating transformer 1 has the end of the secondary winding Ns connected to the anode of a rectifying diode 14. An electrolytic capacitor 15 is connected across the cathode of the diode 14 and the start of the secondary winding Ns.
The output voltage Vo is divided by resistors 16 and 17, and the divided voltage is applied to the inverting input terminal of an operational amplifier 18. A reference voltage generated by a Zener diode 19 and a resistor 20 is supplied to the non-inverting input terminal of the operational amplifier 18. Thus, the operational amplifier 18 compares the voltage applied to the inverting input terminal with the input reference voltage, and adjusts its output voltage, thereby controlling the current flowing through the diode in the photocoupler 12 via a resistor 21. A resistor 22 and a capacitor 23 connected across the inverting input terminal and output terminal of the operational amplifier 18 are provided for adjusting the gain and phase of the closed loop.
First, the input voltage E brings the MOS-FET 2 into conduction because the starting resistors 4 and 5 apply a bias to its gate terminal. Thus, the input voltage E is applied to the primary winding Np, and induces a voltage across the auxiliary winding Nb with the (+) of the voltage being at the start side of the winding. Although a voltage is induced across the secondary winding Ns, the voltage is not transferred to the secondary side because the voltage has its (−) at the anode side of the rectifier diode 14. Accordingly, the current flowing through the primary winding Np is only the exciting current of the isolating transformer 1, and the isolating transformer 1 stores the energy proportional to the square of the exciting current which increases in proportion to time. The voltage induced across the auxiliary winding Nb charges the gate of the MOS-FET 2 via the capacitor 6 and resistors 7 and 8, thereby continuing the conduction state of the MOS-FET 2.
The capacitor 10, which constitutes the time constant circuit with the resistor 11, is charged by the current from the auxiliary winding Nb. When the voltage across the capacitor 10 exceeds Vbe of the transistor 3, the transistor 3 conducts, which reduces the gate voltage of the MOS-FET 2 and brings the MOS-FET 2 out of conduction. Thus, voltages opposing to the voltages at the start are induced across the individual windings of the isolating transformer so that the secondary winding generates the voltage having its (+) at the anode side of the rectifier diode 14. As a result, the energy stored in the isolating transformer 1 is rectified and smoothed, and transferred to the secondary side. When the energy stored in the isolating transformer 1 is completely transferred to the secondary side, the MOS-FET 2 conducts again.
The reason for this is as follows. The voltage proportional to the drain-source voltage of the MOS-FET 2 is induced across the auxiliary winding Nb. On the other hand, immediately after the MOS-FET 2 is brought out of conduction, the gate terminal is biased at (−), and the (−) bias gradually reduces when the transfer of the energy to the secondary side is completed. Thus, the gate terminal of the MOS-FET 2 is biased toward the (+) direction again through the coupling capacitor 6.
The photocoupler 12 increases its current with an increase of the output voltage Vo, and supplies an increasing current to the capacitor 10, thereby reducing the charge time. This reduces the conduction duration of the MOS-FET 2 and the energy stored in the isolating transformer 1, thereby carrying out the constant voltage operation by decreasing the output voltage Vo. When the output voltage is low, the operation is carried out in the opposite direction.
FIG. 6 is a diagram illustrating current or voltage waveforms at various portions of the self-excited flyback converter. In FIG. 6, VG designates the gate voltage of the MOS-FET 2, VDS designates the drain-source voltage of the MOS-FET 2, ID designates the drain current, VNs designates the voltage induced across the secondary winding Ns, IS designates the current flowing through the rectifier diode 14 at the secondary side, and VNb designates the voltage induced across the auxiliary winding Nb.
First, the ON period of the MOS-FET 2 will be described. When the gate bias is applied via the starting resistors 4 and 5, it increases the potential of VG, and brings the MOS-FET 2 into conduction. Accordingly, the current ID increases linearly with time, and stores energy in the isolating transformer 1. In this case, since the MOS-FET 2 is in the conduction state, VDS maintains its potential at nearly zero. On the other hand, although the rectifier diode 14 at the secondary side is supplied with VNs, since it provides the reverse bias, IS is kept zero. The auxiliary winding Nb has the voltage indicated by VNb in this case.
When the capacitor 10 is charged, the transistor 3 conducts and the gate voltage VG of the MOS-FET 2 becomes zero, thereby bringing the MOS-FET 2 out of conduction. Accordingly, ID becomes zero, and VDS equals the sum of the output voltage of the secondary side multiplied by the turn ratio for the input voltage E plus the surge voltage. In this case, the rectifier diode 14 at the secondary side conducts, and the energy stored in the isolating transformer 1 is transferred to the secondary side. The current IS linearly reduces with the negative slope, so that the auxiliary winding generates a negative voltage.
(Operation of DC/DC Converter)
A DC—DC converter is usually used in the power supply system to convert the output voltage from the switching power supply to a desired voltage level. In the conventional power supply system, a step-down DC—DC converter has been widely used as such a DC—DC converter.
FIG. 7 is a circuit diagram showing a basic configuration of the step-down DC—DC converter. The step-down DC—DC converter is placed in the post-stage of the switching power supply unit to generate any specified DC output voltage (V1) from the DC output voltage (Vo) of the switching power supply unit. The step-down DC—DC converter mainly comprises an input capacitor 28, a p-channel MOS-FET 29, an inductor 30, a diode 31, and a rectifier capacitor 32. The p-channel MOS-FET 29 has its source connected to the Vo side, and the drain connected to a first terminal of the inductor 30. The rectifier capacitor 32 is connected across the second terminal of the inductor 30 and the ground GND. On the MOS-FET 29 side of the inductor 30 is connected the cathode of the diode 31 whose anode is connected to GND. A comparator 33 has its output terminal connected to the gate of the MOS-FET 29 via a resistor 34. The non-inverting input terminal of the comparator 33 is supplied with the output voltage (V1) via a resistor 35 as a detection voltage, and the inverting input terminal is supplied with a voltage obtained by dividing the input voltage (Vo) by resistors 36 and 37. When the output voltage supplied to the non-inverting input terminal is lower than the reference voltage supplied to the inverting input terminal, the output of the comparator 33 becomes Low level. Thus, the p-channel MOS-FET 29 conducts, and the capacitor 32 is charged through the inductor 30. When the non-inverting input terminal voltage exceeds the inverting input terminal voltage because of the charge of the capacitor 32, the output of the comparator 33 becomes High level. Thus, the p-channel MOS-FET 29 is brought out of conduction, and the diode 31 conducts, thereby terminating the regenerative cycle of the inductor 30. Repeating the foregoing operation, the DC/DC converter supplies the specified DC output voltage to an apparatus such as a micro-controller.
(Operation of Overvoltage Protection Circuit)
Next, the operation of an overvoltage protection circuit for preventing the overvoltage at the time of an open loop, device destruction or the like in the conventional switching power supply unit will be described with reference to FIG. 5. The Zener diode 25 has its cathode connected to the output side terminal via the resistor 24, and its anode terminal connected to the anode terminal of the phototransmitter side of the photocoupler 26 for transferring a signal. The cathode terminal of the phototransmitter side is connected to the GND terminal.
The MOS-FET 2 has its gate terminal connected to the anode terminal of a thyristor 27 for the latch operation, and its source terminal connected to the cathode terminal of the thyristor 27. The photoreceptor side transistor of the photocoupler 26 has its collector connected to the gate terminal of the MOS-FET 2, and its emitter connected to the gate terminal of the thyristor 27.
If the feedback signal is lost because of the short-circuit between the input terminals of the operational amplifier 18 or because of the device open of the photocoupler 12, for example, the normal closed-loop control becomes impossible, thereby increasing the output voltage. This will bring about a failure in the output side circuit, or action of the explosion-proof valve of the aluminum electrolytic capacitor.
To curb the abnormal increase in the output voltage, the conventional apparatus carries out the protective operation with the circuit including the Zener diode 25, photocoupler 26, thyristor 27 and the like. The operation will now be described.
If the output voltage exceeds the operation voltage of the Zener diode 25 because of an abnormal operation of the closed-loop control, a current flows through the phototransmitter side of the photocoupler 26 via the resistor 24. The current is transmitted to the photoreceptor side of the photocoupler 25, and supplies the gate terminal of the thyristor 27 with a trigger current. Thus, a current flows through the thyristor 27 from its anode to cathode, thereby reducing the gate voltage of the MOS-FET 2. The reduction in the gate voltage halts the oscillation of the MOS-FET 2, thereby reducing the output voltage.
Since the thyristor 27 is supplied with the hold current from the starting resistor 4 side, the MOS-FET 2 continues to halt the oscillation until the AC input is turned off and the hold current is removed. As a result, the output voltage (Vo) is reduced, and the post-stage DC—DC converter stops its operation, reducing the DC output voltage (V1) of the DC—DC converter.
The conventional circuit configuration, however, has a problem of increasing the cost of the components because of the expensive thyristor used for preventing the overvoltage.
In addition, it has a problem of requiring an additional filter circuit to prevent the misoperation of the thyristor due to injection noise.